DRAM devices of the type used in computers and the like are typically each comprised of a matrix array of memory cells. The amount of information that can be stored within each DRAM device is dependent on both the number of memory cells in the matrix array and the number of bits that can be stored by each cell. In one type of DRAM device, each memory cell stores one bit of data while in another type of DRAM device, each cell stores four bits of data. A DRAM device that contains 16M separate cells (where M represents 1,048,576 bits), each cell storing one bit of information, is referred to as a 16M.times.1 device whereas a DRAM device containing 4M cells, each storing four bits, is referred to as a 4M.times.4 device.
Each memory cell within the DRAM device has a unique address that designates the location of that cell in the array. The number of addresses needed depends on the number of cells in the DRAM device. For example, a 4M.times.4 DRAM device requires 4M addresses, each address typically being represented by a twenty-two-bit binary word. Rather than provide the DRAM device with a separate address line for each bit in the binary address, most DRAM devices multiplex their address lines so as to have only as many lines as the largest row address or column address, depending on which is greater.
To locate a particular cell in the matrix array in a DRAM device having multiplexed address lines, a row address, specifying the row containing the memory cell of interest, is first placed on the address lines. The row address is decoded to select the corresponding row containing the specified cell. Thereafter, the address of the column containing the memory cell of interest is placed on the address lines. Similarly, the column address is decoded and the corresponding column containing the cell of interest is selected. The combination of the row address and column address completely specifies the location of each memory cell in the array. In the case of a 4M.times.4 DRAM device having a square array of memory cells (i.e., 2048 rows by 2048 columns), eleven binary bits am required to specify each row address and each column address, thus necessitating eleven address lines. A DRAM device having such a square array of memory cells is said to be symmetric.
Presently, DRAM devices having a density of 4M and greater are being fabricated with a rectangular rather than square array of memory cells, usually with more rows than columns. The benefit of arraying the memory cells in this manner is that the peak energy needed to refresh each row of cells is smaller, because each row has a smaller number of cells as compared to a symmetric DRAM device having the same number of cells. A DRAM device having a rectangular array of memory cells is said to be asymmetric. Unlike a symmetric DRAM device whose row and column addresses are of equal length, asymmetric DRAM devices require a larger row address and a smaller column address. Thus, in the case of a 4M.times.4 DRAM device having a matrix array of 4096 rows by 1024 columns of cells, twelve bits are required to specify the address of each row while only ten bits are required to specify each column address.
In systems that employ a plurality of DRAM devices, the task of addressing the cells in the DRAM devices is performed by a memory controller in response to a cell address provided by a processor or the like. Presently, the memory controllers employed to control banks of DRAM devices are designed to provide the proper row and column addresses for either an asymmetric or a symmetric DRAM device, but not both. Thus, it has not been possible to mix asymmetric and symmetric devices in the same memory bank.
The emergence of asymmetric DRAM devices, and their interchangeability with symmetric devices, makes it desirable to employ both types of devices in a memory bank. In particular, most symmetric and asymmetric DRAM devices of the same density have the same physical appearance so that differentiating between them is difficult. However, given the inability of present day controllers to address both symmetric and asymmetric DRAM devices, it is thus necessary to segregate such devices.
Thus, there is a need for a technique for controlling a memory bank containing asymmetric and/or symmetric DRAM devices.